This invention relates to a signal converter; and, more particularly, it relates to a digital-to-analog (D/A) converter which has a linear input/output characteristic and also to an analog-to-digital (A/D) converter of the successive approximation type which employs the D/A converter as a local decoder.
A linear D/A converter or A/D converter is an important constituent of the input/output circuit of each of various control systems which utilize digital data processors, for example, computers. Such a converter has heretofore been known in various forms.
One of the well-known converters of this sort is the weighted capacitance type converter, which uses an array consisting of a plurality of capacitors having binary-weighted capacitance ratios. In this case, the capacitors correspond to the respective bits of a binary word. The ends of the capacitors on one side are connected to a single signal line in common, while the other ends are selectively connected to a reference voltage supply line or a ground voltage supply line through respective switches. In this converter, the switched are turned "on" and "off" in conformity with the pattern of the binary word. The capacitors corresponding to the bits having the binary value "1" are connected to the reference voltage, and the other capacitors are connected to ground, whereby an analog voltage corresponding to a digital value is generated on the signal line.
Since capacitor elements can be formed on a semiconductor substrate at a comparatively-high relative accuracy by utilizing the technology used for producing MOS devices, the weighted capacitance type converter brings forth the advantage that a conversion characteristic of excellent linearity is attained. However, when it is intended to fabricate a converter of high resolution with this type of construction, there is the problem that the semiconductor substrate requires a large area in order to form a capacitor array having correct binary-weighted coefficients.
By way of example, the capacitor array of the correct binary-weighted coefficients may be fabricated in such a way that a large number of capacitor elements each having a unit capacitance are formed and that the capacitor elements in numbers corresponding to the weighted coefficients are combined to form the capacitors of the respective bits. With this measure, however 2.sup.n unit capacitors are needed for a converter which has a resolution of n bits. On the other hand, when it is intended to form the capacitors of the respective bits in the shape of individual capacitor elements of unequal areas, it is necessary to make the size of the capacitor of the least-significant bit (LSB) large to some extent and to precisely determine the sizes of the other capacitors with reference to the first-mentioned size, in order to suppress within a prescribed range the errors of the capacitance ratios of the capacitors ascribable to manufacturing techniques. If it is intended to obtain the capacitor array of the binary-weighted coefficients with the capacitor of the LSB set at a small capacitance, it is feared that the binary coefficients will not become correct on account of the manufacturing errors and that the variation of analog values will become nonmonotonic versus the continuous increase of digital values in one direction. Such disorder of the monotonicity degrades the differential linearity of the A/D converter, and limits the usage thereof.
As another type of converter, there has been known the resistor string type. In the converter of this type, a reference voltage is equally divided by a resistor string so as to derive a divided voltage corresponding to a binary word. The selection of the divided voltage can be effected through a plurality of switches connected in the shape of a matrix as disclosed in, for example, Japanese Patent Application Laying-open No. 52-28851 (U.S. application Ser. No. 608,873).
The switching matrix disclosed in the laid-open specification has N current paths which are connected to protrusions of the resistor string, and each of which includes n switches fulfilling the relationship N=2.sup.n. The switches are turned "on" and "off" by control signals which correspond to the respective bits of the binary word.
With the resistor string type converter, one of the N voltages divided by the resistor string is selected in correspondence with the binary word, and hence, there is the advantage that the monotonic increase of analog output voltages versus the increase of digital values is ensured. However, the resistance values of resistor elements which are formed on a semiconductor substrate vary depending upon the shapes thereof or due to external pressures acting on the substrate. Therefore, even when it is intended to fabricate a converter of high resolution with this type of construction, it is difficult to form a resistor string of uniform resistance distribution, and a problem is posed in the linearity of the input/output characteristic.
A converter with the weighted capacitance type characteristics and the resistor string type characteristics combined has also been known in a coder and a decoder for PCM signals having nonlinear input/output conversion characteristics. For example, the IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 1, February, 1979, pp. 65-73, has introduced a converter (CODEC) wherein a compressed quantizing characteristic of .mu.=255 is approximated by 15 chords (or segments) and wherein eight segments of each of the plus and minus polarities are determined by a capacitor array, while sixteen steps within each segment are determined by a resistor string. In this case, the capacitor array consists of eight capacitors having binary-weighted capacitance ratios (coefficients). The capacitors from that of the smallest coefficient to that of a coefficient value which is assigned by the upper three bits of a binary word except the sign bit thereof are supplied with a reference voltage, the capacitor of the upper bit adjoining the capacitor of the assigned coefficient value is supplied with a divided voltage which corresponds to the lower four bits of the binary word and which is obtained from the resistor string, and the other capacitors are supplied with ground potential.
When, in the construction of the CODEC, the capacitors of the capacitor array are made to have equal capacitances, a linear quantizing characteristic can be attained. With this construction, however, that number of capacitors which is equal to the number of segments are required, and a converter in which the upper n bits of the binary word are allotted to the segment assignment needs as many as 2.sup.n capacitors. In addition, the construction requires three switches for selectively supplying the reference voltage, the divided voltage and the ground voltage to the capacitors, respectively, so that an increase in the number of capacitors trebles the number of switches. As a result, in order to increase the segment assignment bits from three bits to four bits by way of example, eight capacitors and twenty-four switches need to be added. In this manner, the increase of the circuit elements required for the resolution enhancement of only one bit becomes enormous.